Mixed-Signal Escape Routing Algorithm for Multilayer PCBs

As manual escape routing is becoming a time-consuming and error-prone task because of the increasing densities in printed circuit boards, automatic escape routing has recently gained a considerable amount of attention as an alternative solution. However, there are a variety of design requirements, and conventional methods cannot fulfill some of them. In this paper, we present a new mixed-signal escape routing method to alleviate these issues. First, the proposed method enables the relaxation of the length-matching constraints. It is difficult to reflect this requirement in a conventional two-step approach in which merging point selection and merged signal routing are treated as two independent problems. Therefore, we newly formulate the above-mentioned two phases of differential pair routing into a single optimization problem and encode this constraint. Second, we develop constraints for power and ground nets, which are first escaped to lower layers through vias and connected to the corresponding power/ground regions. In this process, the merging of the same types of power/ground nets is sometimes needed for better space usage. To this end, we develop a formulation allowing the merges of the same type of nets. In addition, our formulation supports two types of via connections. Although conventional methods usually assumed the via-in-pad condition and developed formulations, the via-in-tile condition, termed in this paper, is still used in the industry because of its cost effectiveness. The experimental results on real-world examples showed that our escape routing method successfully routes out signals and can replace or help with cumbersome manual routing processes.