Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA

Physically unclonable function (PUF) is one of the most advocated security primitives which extracts the uncontrollable intrinsic physical property of the fabrication process to generate secret bits for authentication, random number generation and key generation. Ring oscillator (RO) PUF is the widely adopted PUF design to implement in FPGA platform, but it is highly error prone to environmental noise (i.e. temperature and voltage). The configurable RO (CRO) PUF is advocated to resolve this issue without increasing the area overhead. This paper proposes an enhanced CRO framework which uses latch instead of inverter to build an RO. The use of dedicated latch (i.e. available in an FPGA) in place of inverter eliminates the restriction to use odd number of delay units (inverters) in an RO configuration. The proposed design efficiently utilizes the resources found in a configurable logic block (CLB) to increase the number of RO configurations while using the same area. Also, it provides the flexibility to include a latch in an RO configuration which in turns improve the reliability and the security as well. Experimental results on Xilinx Spartan 3E FPGA establish that the proposed design exhibits high stability despite varying environmental conditions without using any error correcting code or post-processing technique.