Design and Characterization of Two Different Structure of Junctionless Nanowire Transistor Considering Quantum Ballistic Transport Model

In this work, the performance of two different structure of double gate junctionless nanowire transistor (DG-JLNT) has been analyzed. The conventional junctionless double gate (JLDG) and the modified flared up source and drain with submerged gate electrode structure are analyzed using Non-Equilibrium Green's Function (NEGF) approach by TCAD Silvaco Atlas. As the NEGF approach shows better accuracy than other approaches in quantum modeling simulation for smaller channel length, this work was conducted depending on this approach. Performance parameter named Drain Current (I
_D
), Threshold Voltage (V
_th
), Subthreshold Swing (SS), on state and off state current ratio (I
_on
/I
_off
) for the mentioned structures of n-channel JLDG transistor are analyzed. Simulation has been performed by varying channel length (L
_g
) and oxide thickness (T
_ox
) to observe the electrical characteristics. In order to observe Short Channel Effects (SCEs), the above parameters were investigated. In essence, flared up JLNW transistor showed better SCEs performance in current on state and off state (I
_on
/I
_off
) ratio and lesser Threshold Voltage Roll Off (TVRO) over channel length variation. But in other SCEs parameters like SS and Drain induced barrier lowering (DIBL), conventional JLDG is pictured as the better candidate.