FPGA-Based Real-time Interference Alignment Verification System

We propose a FPGA-based real-time interference alignment (IA) verification system by combining multiple F-PGA from a software defined radio (SDR), where the high-level hardware description language (HDL) and the modular design are adopted. The system exhibits excellent scalability, utility and flexibility in the development of the IA verification system, and reduces the computational amount and complexity of implementing IA technology. Referring to IEEE 802.11a physical protocol data unit (PPDU) frame structure, this paper designs a unique physical frame structure to obtain the global channel status information (CSI). To demonstrating the IA verification system, this paper detailed describes the accomplished procedure based on the proposed system architecture at SDR.