Design of a Rectifier-Free Near-Threshold UHF Gen2 RFID Tag using Dual-Phase RF-only Logic

Conventional RFID circuits use area-inefllcient rectillers and storage capacitors, and the latter do not scale with technology. These blocks can be eliminated by using a costefllcient RF-only logic approach, which introduces a power consumption trade-off. This paper presents the design, implementation, and post-layout simulation results for a near-threshold voltage, area-efllcient Gen2 compatible RFID tag using dualphase RF-only logic. The RFID tag is designed in a 130nm CMOS process, where NTV operation enhances input sensitivity by reducing power consumption. Dual-phase RF-only logic circuits are advantageous over single-phase circuits since they can operate at >2x speed and power conversion efllciency for the same RF supply. A custom standard cell library operating at 550mVpp RF supply voltage is developed, where device sizing relies on reverse short channel effect and body biasing technique. Simulations show successful operation for a 550mVpp RF supply, with an input sensitivity of -1.2dBm and the analog blocks consuming a low power of 14μW. Compared to a single-phase RFID design operating on a 1Vpp RF supply in the same process, this is a 4.5dB improvement in sensitivity, and the area increases by only 17%. These results demonstrate the feasibility of power-efllcient RF-only logic implementations for future cost sensitive RFID applications.