Instructions with Indirect Register Indexing for Multiple and Exponential Operations to Improve Performance

The current multi-core systems cannot be made scalable to large number of processors due to limited memory bandwidth needed to deliver instructions and data to many processors at the required rate.We propose a method that is capable of enhancing the power of a single instruction to perform multiple or exponential number of operations on data in registers that maps to any location in memory. The enhanced features of instruction are hidden from pipeline until the execution stage, creating a virtual effect of executing single instruction to simplify the microarchitecture and reduces the demands for fetching multiple instructions or accessing data elements. The method uses multiple function units that exist in any conventional processor, to perform these operations referenced by indirect register indexing in single cycle at the same time.