A multi-phase detecting method for spurs cancellation in all digital fractional-N phase-lock loops

The fractional spurs of All Digital Phase-lock Loops (ADPLL) is limited by the resolution and linearity of the time-to-digital converter (TDC). Although a high resolution narrow range TDC can be achieved in digital-to-time converters (DTC) assisted ADPLL, it actually shifts the nonlinearity issue to the DTC block, which may also bring unwanted spurs. In this paper a multiphase detecting method is proposed for the cancellation of the spur caused by the nonlinearity both from DTC and TDC. The proposed multi-phase detecting architecture contains an inherent finite impulse response (FIR) filter to suppress the fractional spur. What's more, the FIR filter can adapt to the frequency variation of fractional spurs. The simulation results show that this method significantly eliminates fractional spur without adding other noise.