Analysis of Package Impedance Effects on the Linearity of Source Series Terminated DACs

This paper proposes a digital pre-distortion compensation technique canceling the package impedance effect on a 10-bit source series terminated (SST) digital-to-analog converter (DAC) implemented in 28nm CMOS with a 1.8V power supply. Given the data-dependent power supply current of a source series terminated DAC, any power supply and package impedance introduces non-linearity behavior fundamentally limiting the achievable SFDR. In order to be able to cancel this impact, first of all the package impedance as well as the power supply grid is analyzed and a parametric expression is derived for the oscillation frequency and damping of the power supply. Based on this model, a hardware-efficient pre-distortion cancellation technique using an 5-bit auxiliary DAC is proposed which improves the SNDR by 8 dB at low input frequencies and >4 dB at Nyquist frequency. In addition, a pure digital correction method is introduced and compared to the AUX-DAC solution. The mathematical model is verified by detailed full transistor-level simulations. The obtained results prove the potential of such a strategy for mitigating the effects of the power supply impedance and bondwire parasitics, therefore, enabling the use of inexpensive packaging technologies for high accuracy SST DACs.