A Low-complexity Hardware AWGN Channel Emulator on FPGA using Central Limit Theorem

We present a flexible, low-complexity additive white Gaussian noise (AWGN) channel emulator. The proposed generator employs multiple improved Tausworthe generators to generate uniform random numbers, which are then summed up and manipulated based on the central limit theorem to generate Gaussian random numbers. We simulated the hardware design with 12 and 48 Tausworthe random number generators (RNGs) with different seed sets. The proposed design provides one sample per clock useful towards high speed channel emulation.