FPGA Implementation of Face Recognition System Based on Convolution Neural Network

This paper presents a FPGA implementation of face recognition system based on convolution neural network. The hardware architectures for convolution layers, pooling layers, full-connected layer and softmax layer are designed. In each convolution layer, the parallelisms among convolution kernels and among feature maps are explored, and the convolution operations are carried out in parallel. The pooling operations for different feature maps are also computed in parallel. The Verilog HDL modules for the architectures are designed, simulated and synthesized to FPGA. The result shows that the architectures designed in this paper are correct and effective.