A Novel 8T SRAM Cell with Low Swing Voltage for Portable Devices

Power minimization is a critical concern for the battery operated fast devices. This paper presents a low voltage swing static random access memory (SRAM) structure with eight MOS transistors which consume a lesser amount of dynamic power at a higher frequency and also has a higher stability as compared with the models reported in the existing literature. The proposed SRAM consists of voltage source which helps to reduce the required swing voltage during the switching activity at the output nodes. Simulated results of static noise margin and dynamic power at different frequencies have been calculated for the proposed design and are compared with various reported SRAM designs. 22nm CMOS technology is used for the simulation purpose.