A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines

A new digitally controlled shunt-capacitor inverter delay element and its design procedure are presented. The digital shunt-capacitors consist of binary scaled transmission gates and have a much smaller total capacitance and resolution than state-of-the-art solutions using separate MOSFETs for switches and capacitors. This results in a lower power consumption and smaller area making the shunt-capacitor inverter an efficient solution for high-resolution delay lines in the GHz range. Different topologies for the MSB and LSB shunt-capacitors further improve the efficiency by reducing the minimum capacitive loading of the CMOS inverter. The proposed delay element is verified in a 65 nm CMOS process implementing a four stage delay-line with a step size of 0.82 ps in a 2.5 GHz all-digital multiphase delay locked loop.