Direct Digital Frequency Synthesis design methodology for optimized spurs / jitter performances

The paper presents a simple methodology to choose the main parameters of Direct Digital Frequency Synthesis (DDFS) to fulfil the requirements of a given communication protocol. The set of parameters are chosen in function of the jitter and thus the BER and leads to some Digital to Analog Converter (DAC) phase noise limits. The method described relies on a Matlab algorithm that calculates the output tones of the DDFS. The latter consists of a phase accumulator, a lookup table, a DAC and a low pass filter. The algorithm permits to define the main parameters of the DDFS blocks such as the clock frequency, the number of bits in the accumulator and the lookup table memory. On the same way the DAC number of bits and the attenuation and filter bandwidth can be estimated in order to evaluate the output performances in terms of frequency resolution, jitter and spurs noise. In our application, the frequency synthesizer must ensure a frequency step of 100 Hz, a fast settling time of 200 ns, a jitter of 300 ps in the 10 kHz - 1 MHz bandwidth and the spurs amplitude must be -70 dBc at 2 MHz frequency offset from 1.4 GHz output frequency. The simulations give an insight of the challenges to be taken into account at the initial stage of the integrated circuit design.