28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning

This paper presents low-power and low-energy 8T dual-port SRAM with a novel MSB-based (most-significant-bit-based) inversion logic for an image processor such a deep-learning processor. Our proposed SRAM is suitable for real-time and low-power image processing, in which data have statistical correlation and data bit reordering are exploited. The proposed MSB-based inversion logic eliminates an additional flag bit in a majority logic; the MSB digit in an input datum judges whether or not to invert the datum. Thus, the area overhead of 12.5% for the 8-bit conventional majority logic is dramatically saved. The area overhead of the proposed SRAM is merely 0.6% for the MSB-based inversion logic. We verified that, with the proposed technique, 14.76% of total energy can be saved in a 28-nm 64-kb FD-SOI SRAM when a set of images are read out. Furthermore, the saving factor is extended to 17.31% when image processing in the VGG-F convolutional neural network (CNN) is considered, where 304.81 fJ/cycle in the read operation is achieved.