Design-dependent Monitors Based on Delay Sensitivity Tracking

Design-dependent timing monitors are used on-chip to trace the timing variability of critical paths w.r.t. process, voltage and temperature (PVT) fluctuations. A sensitivity-based design-dependent timing monitor mimics the timing behavior of a group of critical paths by matching their delay sensitivities. With the target of fortifying the existing design-dependent ring oscillators (DDROs), different algorithms for sensitivity matching are investigated in this work. Moreover, different methods for characterizing the building blocks of DDROs are thereby exploited and a method to evaluate the quality of synthesized DDROs is described. An industrial technology node below 40nm is used for evaluating the presented approach.