An Efficient Uniform-Segmented Neuron Model for Large-Scale Neuromorphic Circuit Design: Simulation and FPGA Synthesis Results

Large-scale simulation of spiking neural networks on hardware with a remarkable resemblance to their mathematical models is a key objective of the neuromorphic discipline. This issue is, however, considerably resource-intensive due to the presence of nonlinear terms in neuron models. This paper proposes a novel uniform piecewise linear segmentation approach for nonlinear function evaluations. Employing the proposed approach, we present a uniform-segmented adaptive exponential neuron model capable of accurately producing various responses exhibited by the original model and suitable for efficient large-scale implementation. In contrast to previous nonuniform-segmented neuron models, the proposed model enjoys a high-speed and extremely simple segment address encoder unit regardless of the number of segments. Simulations and hardware implementations on FPGA confirm that the proposed model significantly outperforms previous works in terms of resource utilization, accuracy, and maximum clock frequency. Moreover, employing the resource sharing technique, a fully pipelined hardware-efficient network containing one neuron circuit is proposed aimed at simulating a large number of neurons in both real and accelerated time scales. To assess the performance of the proposed network as a high-speed accelerator, four networks composed of 1k to 4k neurons are simulated using both FPGA and standard PC workstation. Results demonstrate that the proposed fully pipelined network accelerates the simulation process, on average, 89.96 times compared with the computer-based simulation.