A Fault Propagation Model for FPGA Netlist with Un-Reconvergence Paths

In this paper, we propose an analysis method of fault propagation based on the FPGA netlist with un-reconvergence path. First of all, we analyze the characteristics of common components in the netlist, calculate the fault propagation probability of these components, and then establish a netlist-level fault propagation model based on the interconnection topological structure of the components in the netlist. When a fault happens at input ports of the netlist, we analyze the fault propagation characteristics in the whole netlist, calculate the probability of the fault propagating from input to output ports, and find out the input port which is most likely to cause the fault. Finally, we verify the model presented in this paper by experiments. The experimental results show that the estimated error of fault propagation probability is negligible. It is less than 0.1% compared to the corresponding testing results.