Design of GaAs MMIC transistors for the low-power low noise applications

The paper investigates the problem of minimizing bias power for low noise GaAs amplifiers. The model of the amplifier parameters versus transistor gate width is presented and used to derive the conditions for noise optimization. It is shown that optimum FETs are rather wide and may operate at very low current densities. Complete amplifier stages with only 3-5 mW bias power are feasible at 2 GHz with noise figures below 1 dB.