Modeling and Simulation of Novel Ferroelectric Gate Stack in MOSFET for Enhanced Device Performance

Ferroelectric (FE) materials have seen increasing interest from the semiconductor industry with a focus to utilize their high permittivity and polarization properties. Of particular interest is the integration of high-k FE dielectrics in the gate structure of transistors to improve their performance. This work proposes a novel MOSFET in 45 nm technology, which integrates a thin layer of BaTiO3 (BTO) in the gate structure to significantly improve the drain current in saturation region without adverse effects to sub-threshold slope. A finite element TCAD model of the proposed transistor is developed to analyze the device performance and investigate the effects in threshold voltage and gate capacitance. The integration of the BTO layer in combination with a Hafnium Oxide (HFO2) buffer layer in the device minimized the hysteresis effect and exhibited a 43% improvement in drain current while lowering sub-threshold gate leakage. A Spice simulation based on the TCAD model was performed to demonstrate the impact of the reported performance gains in the context of an inverter. The results indicate promising application of the proposed transistor model in high performance logic designs.