A Quasi-Analytic Behavioral Model for the Single-electron Transistor for Hybrid MOS/SET Circuit Simulation

A methodology to incorporate single-electron transistors (SET) into the IC design flow is introduced in this paper. A SET model is developed that is defined as a VERILOG-A module that can be used for SPICE-like simulation of hybrid circuits containing SET and MOS transistors. The SET model is formulated in a semi-symbolic form, which provides insight and intuition on the functionality of the device. The model was verified on a SET-only and hybrid (SET and MOS transistors) implementation of an inverter. The proposed model is compared with a verified analytical model that applies a master equation, which results in errors of approximately 1.6% for a SET-only inverter and 1.3% for a hybrid inverter.