40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate

A 2×VDD I/O buffer featured with PVT (process, voltage, temperature) corner detection and SR (slew rate) auto-compensation is proposed. Besides, a nonoverlap timing control is added to the gate drives of those large devices in the output stage such that the appearance of possible DC current spikes caused by simultaneous turn-on driving MOS transistors is prevented. Not only is the SR enhanced, the power dissipation is also reduced. The maximum data rate is 2.5/1.6 GHz given 0.9/1.8 V supply voltage with 20 pF load, respectively, by all-PVT-corner simulations. The Δ SR improvement is 31.9%(rising)/48.9%(falling) and 26.0%(rising)/41.0%(falling) for 1×VDD and 2×VDD, respectively, when the proposed PVT auto-compensation design is activated.