P-Edge NMOSFET for Improving TID Tolerance

This letter proposes a novel device structure named P-edge nMOS, in which high P+ doped belts are placed at the edges of the N+ source and drain. This structure is immune to the radiation-induced edge effects, thus, is able to improve total ionizing dose tolerance with much less area cost than enclosed layout transistors. Furthermore, P-edge nMOS is fully compatible with standard commercial technologies and can be used as a technique of radiation hardened by design. In order to evaluate the radiation tolerance of the new structure, sample transistors fabricated by the SMIC 350-nm commercial CMOS process with shallow trench isolation have been irradiated up to total doses of 2 Mrad(Si). The experimental results show that the leakage current of the P-edge nMOS is four orders of magnitude smaller than the normal nMOS device and the threshold voltage variation of the P-edge nMOS is reduced by about 90% when the dose is up to 2 Mrad(Si). The proposed P-edge nMOS can be a competitive alternative device to be used in CMOS integrated circuits for space applications.