A compact modular architecture for high-speed binary sorting

A new algorithm and a new modular architecture are presented for the realization of high-speed binary sorting engines, based on efficient rank ordering. Capacitive threshold logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The overall complexity of the proposed bit-serial architecture increases linearly with the number of input vectors to be sorted (window size=m) and with the bit-length of the input vectors (word size=n), and the sorter architecture can be easily expanded to accommodate large vector sets. Detailed simulations indicate that the sorter structure can operate at sampling clock rates of up to 50 MHz, where the throughput is boosted by fine-grain pipelining. It is demonstrated that the proposed sorting engine is capable of producing a fully sorted output vector set in (m+n-1) clock cycles.