Pass logic circuits with reduced switching activity for low power DSP processors

There is a tremendous need for miniaturization as well as low power consumption in many signal-processing systems, especially when they are used in portable equipment. In this context, the design of low power DSP processors receives utmost importance. A clever means of achieving this is by use of pass logic circuits in these designs. But switching activity is found to be a major contributor in dynamic power consumption. Hence, a formal technique for calculating the switching activity in CMOS pass networks is presented in this paper, which is validated using various designs of CMOS full adder cells. This technique can therefore be used for the design of CMOS pass networks, with reduced switching activity, suitable for use in DSP hardware for the design of smaller and energy-efficient DSP processors.