Pipeline architecture for 8/spl times/8 discrete cosine transform

An array processor architecture for the 2-D discrete cosine transform (DCT) based on the row-column decomposition of the 2-D DCT. The utilized 1-D DCT architectures are derived by applying the principles used to construct pipelined fast Fourier transform architectures. In general, this approach has not been used due to the irregularities found in the fast DCT algorithms. The basis of our architectural derivation is the constant geometry fast algorithms for DCT described earlier. By rescheduling the operations; an in-place algorithm can be obtained, which can be mapped onto a pipelined structure with the aid of vertical projection. In addition, a sequential matrix transposition network is described, which is based on shift-exchange units.