A parallel complex divider architecture based on DCD iterations for computing complex division in MVDR beamformer

This paper presents a hardware architecture using mixed pipeline and parallel processing for complex division based on dichotomous coordinate descent (DCD) iterations. The objective of the proposed work is to achieve low-latency and resource optimized complex divider architecture in adaptive weight computation stage of minimum variance distortionless response (MVDR) algorithm. In this work, computation of complex division is modeled as a 2×2 linear equation solution problem and the DCD algorithm allows linear systems of equations to be solved with high degree of computational efficiency. The operations in the existing DCD algorithm are suitably parallel pipelined and the performance is optimized to 2 clock cycles per iteration. To improve the degree of parallelism, a parallel column vector read architecture is devised. The proposed work is implemented on the field programmable gate array (FPGA) platform and the results are compared with state-of-art literature. It concludes that the proposed architecture is suitable for complex division in adaptive weight computation stage of MVDR beamformer. We demonstrate the performance of the proposed architecture for MVDR beamformer employed in medical ultrasound imaging applications.