Co-Simulation Testbed for Unbalanced Fault Ride Through Hardware in the Loop Validation

This paper presents the Hardware-in-the-Loop (HIL) platforms validation for a fault ride through control strategy. The proposed fault ride through (FRT) control strategy is to be embedded in the inverter-based interface, based on a phase-coordinating approach. It is conducted on the $abc$ phase coordinates frame rather than the traditional $dq$ synchronous reference frame. A generalized reference current calculation method is developed for tackling the unbalanced FRT scenarios. By utilizing the co-simulation interfaces between Opal-RT and RTDS. This paper validates the proposed FRT control using the combined HIL platforms.