Efficient Dynamic Router Architecture for Optimized Performance of NoC Systems

On chip interconnects are the integral part of System on Chip (SoC). As the technology shrinks with size, wire delay increase and became difficult to meet timing. Network on Chip is the emerging technology and sees as the possible solution to this problem. Routers are the key components in the NOCs. Buffers inside the router are the critical for the energy utilization and for performance improvement, so analysis in reducing fifo depth inside the Router is a key thing in silicon industry. In this paper, proposed a Linked list memory architecture instead of a multi fifo approach for supporting multiple virtual channel architecture. Through this internal buffer architecture, circuit can reduce the area, power and also will able to achieve high throughput and low latency in computational interconnects used in multi core and multi-processor systems with cost effective implementations. This new buffer architecture provides the efficient storage for multi data length packets. We have implemented Clock gating circuit on this for improving the power, added the error termination logic for getting better functionality in address decoding errors and also quality of service (Qos) can be improved.