Power, Performance and Area Optimization of I/O Design

The VLSI (Very Large Scale Integration) industry has been growing constantly obeying Moores law to an extent where multiple processors can be implemented on a single chip. Yet, the development is unable to keep up with the demands and challenges faced by the growth of device capacity in terms of VLSI design without sacrificing the quality. There is a need to produce an efficient placement solution that can address high quality placement. This paper investigates physical design methodologies for synthesizing and optimization of design in terms of power, performance and area by completing the ASIC (application-specific integrated circuit) design flow using advance industry level tools.