Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration

The TULIPP project aims to facilitate the development of embedded image processing systems with real-time and low-power constraints. In this paper, several adaptive dynamic runtime techniques for reconfigurable SoCs are described. These methods are used for low power image processing applications on high-performance embedded platforms. Dynamic voltage scaling and dynamic partial reconfiguration target the low-power requirements of the embedded systems while debugging supports the fast development on the hardware side of the system. The proposed techniques were tested and verified using an own developed custom SDSoC image processing library.