A Novel 10T SRAM cell for Low Power Applications

This paper represents a novel ten transistor based static random access memory (SRAM) architecture with high read noise margin for low power applications. The novel 10T SRAM cell architecture has been designed, using cadence virtuoso tool in 45 nm CMOS technology. Its performance characteristics such as read/write delay, leakage power dissipation, read stability, write-ability, Static Noise Margins have been examined and compared with different 6T and 8T SRAM cell architectures. The simulation results reveal appreciable improvement in stability, read behavior and consumes least power at the cost of area overhead. The proposed cell has a Read Noise margin of 220 mV while for the conventional 6T cell it is 80 mV. Energy efficiency for the proposed P10T cell is found to be 4.07 eV while for the conventional 6T it is 4.87 eV. All simulations have been carried out at 0.4 volts supply voltage.