Architectures and Design Techniques of Digital Time Interpolators

This paper provides an in-depth review of the principle, architecture, and design techniques of digital time interpolators. An assessment of the advantages and drawbacks of analog time interpolators are presented first. It is followed with a comprehensive examination of reported digital time interpolators including gated inverter time interpolators, harmonic-rejection time interpolators, voltage-division time interpolators, and pipelined time interpolators. The design considerations of digital time interpolators including input signaling, output signaling, input-output isolation, and shoot-through are studied in detailed. The performance of recently reported digital time interpolators is compared. Finally, a 5-bit digital-to-time converter with 2-bit time interpolation is designed in a TSMC 65 nm 1.0 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4.4 device models. Simulation results are presented.