Research of Low Inductance Loop Design in GaN HEMT Application

High electron mobility transistor (HEMT) is one popular research topic in the field of power electronic devices. Gallium Nitride (GaN) HEMT has the advantages of high slew rate and low operation loss. In high frequency application, parasitic impedance introduced from PCB layout can have huge impact on operation efficiency and reliability. Minimizing the loop inductance is important. In this paper, three different low inductance loop design methods are analyzed and compared in details. Numeral comparison based on finite elements analysis (FEA) is carried out. Double pulse test is carried to verify the idea. Simulation and experimental results of switching transient are given for comparison. Low inductance loop design is further corroborated by the switching loss and switching time characterization.