Energy-efficiency bounds for noise-tolerant dynamic circuits

Presented in this paper are lower bounds on energy-efficiency of the mirror noise-tolerant dynamic circuit technique. These lower bounds are derived by solving an energy optimization problem subject to an information-theoretic constraint. Design overheads associated with the noise-tolerant circuit techniques are discussed and incorporated into the optimization problem. Simulation results for a 3-input OR gate transferring information at a rate R=150 M bit/s in 0.35 /spl mu/m CMOS indicate that the lower bound on energy consumption of the noise-tolerant circuit is 25 f J/bit, which is 31% below that of the conventional domino circuit. This lower bound is achieved when the noise-immunity of the mirror technique is 1.64/spl times/ more than that of the domino circuit technique.