A semi-formal methodology for the functional validation of an industrial DSP system

This paper describes a new methodology allowing one to increase the efficiency of functional validation. The approach is based on a combination of simulation and formal techniques. It consists of first building formal models of digital hardware modules. The coverage of a test suite can then be accurately measured and new test cases are automatically generated to increase the coverage. This methodology has been applied during the development of a commercial DSP system. It has shown that, in spite of a very large test suite consisting of 300 million simulation cycles, there was still room for coverage improvement.