Trapped charge cancellation for CMOS ISFET sensors via Direct Tunnelling

In this paper Direct Tunnelling current has been used as a mechanism to cancel the Trapped Charge commonly found in unmodified CMOS ISFETs. Our analysis has shown that PMOS devices could be used, having minimum leakage current in normal operation whilst providing considerable large tunnelling current for compensation with gate biasing. We integrate a flip-flop into each sensing pixel to allow self-locking of the gate bias during the charge cancellation process. Our analysis shows that we can use the proposed approach to cancel the trapped charge within 10 minutes, introducing only lu V /s of drift at the output. We demonstrate this mechanism with a 4×4 sensor array operating with a 3-step cancellation process and include simulation results showing the charge cancellation mechanism.