A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range

This paper proposes a fast auto frequency calibration (AFC) technique for wideband PLL with wide reference frequency range. The AFC circuit block adopts a proposed clock controller and a current-mode logic (CML) divider-by-2 divider to accelerate the AFC process without the penalty of AFC resolution. It also adopts the adjustable AFC counting period technique to speed up the AFC process at low reference frequency and to reduce AFC time variation within wide frequency range of reference clock. A 0.1~5 GHz ΔΣ fractional-N PLL with this AFC technique is designed and implemented in 65-nm CMOS process. The measurement results show that in the reference frequency range from 15 to 50 MHz, the AFC time varies only from 1.25 to 1.86 μs with AFC resolution range from 3 to 5 MHz.