An 8/spl times/8 adiabatic quasi-static CMOS multiplier

This paper presents a new type of adiabatic logic. The new adiabatic circuit is named Adiabatic Quasi-Static CMOS (AqsCMOS), because the output is quasi-static. The AqsCMOS is totally compatible with conventional CMOS. Designers can easily reduce the power budget by replacing all or part of an existing CMOS circuit with AqsCMOS circuits to achieve for low power operation. We have designed and fabricated an 8/spl times/8 AqsCMOS multiplier to demonstrate the operation of AqsCMOS. The simulation results have indicated that the new AqsCMOS 8/spl times/8 multiplier consume 90% less power compare with a conventional 8/spl times/8 multiplier of similar architecture.