Low power, area efficient programmable filter and variable rate decimator

A new flexible architecture is proposed for word-serial filtering and variable rate decimation/interpolation. The architecture is targeted for low power applications requiring medium to low data rate and is ideally suited for implementation on either an ASIC or an FPGA. It combines the small size and low power of an ASIC with the programmability and flexibility of a DSP. An efficient memory addressing scheme eliminates the need for power hungry shift registers and allows full reconfiguration via a single ROM. The decimation ratio, filter length and filter coefficients can all be changed in real-time. The architecture takes advantage of coefficient symmetries in linear phase filters and in polyphase components.