Design Trends and Challenges of Advanced Waferlevel Manufacturing and Fanout

Fan-out is arguably the fastest-growing advanced packaging technology, driven predominately by mobile processing and wireless. These designs often contain single large die, or multiple die, yet are limited in the number of available routing layers. Without the benefit of high layer counts and with substrates not much larger than the die extents, providing the ability to plan and optimize the design can significantly and positively impact the ability to provide a routable solution. This paper will discuss the challenges of designing a large FO-WLP device, as well as the capabilities required to plan, optimize, and implement the interconnect in the design in as few layers as possible. We will discuss the challenges at each phase of the design: from initial system planning and feasibility, assignment, early SI analysis, optimization and implementation, and finally sign-off.