Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features

Clock power accounts for between 15% and 30% of a chip's power budget today. Due to this reason, demands for reducing power consumption makes dual-edge clocking attractive. However, clock domain crossings (CDCs) in dual-edge logic poses some unique problems for commonly used DFx features. Solutions such as lock-up latches are not directly applicable. First, scan-chain CDCs are considered for which two solutions are presented. Second, two problems related to clock-stoppage for scan-dump are considered and solutions to these problems are proposed and analyzed.