Approximate computing for 4-bit Adder Design

In this paper, an approximate logic synthesis (ALS) method target for circuit area reduction is proposed for adder design. The method include the approximate function description of the adder and the circuit area evaluation which are realized by genetic algorithm (GA) and logic effort. The method is applied for 4-bits adder design. And experimental results show that proposed approximate adder has 19.19% area improvement with less than 0.12% error rate introduced. When using Library-free mapping technique, the area is further reduced to 26.25%.