A high-speed dynamic comparator with low-power supply voltage

Generally, a dynamic latch comparator may include two inverters configured back to back to latch the result of comparison. One of the major factors affecting its speed is the power supply voltage, because the maximal Vgs (gate-source voltage) of MOS devices is power supply voltage. In this paper, a new structure of dynamic latch comparator is proposed for high-speed applications with low-power supply voltage. Each inverter includes a capacitor that decouples the gates of the PMOS and NMOS devices. Thus, the maximal Vgs is beyond what is allowed by the low-power supply voltage. The disclosed comparator is compared with previous dynamic comparators. For the same size of input/output transistors and latch as well as load capacitance with a 0.7 V power supply voltage, it achieves a x2 improvement in speed. Low-power technique is also adopted to reduce the power consumption of the latch. Therefore, the proposed comparator shows better performance in both speed and low power consumption in low-power supply voltage.