An 11-bit 350MS/s 2b/cycle-Assisted SAR ADC with Improved Comparator Clock Generator

A successive-approximation-register (SAR) analog-to-digital-converter (ADC) architecture with hybrid 2b/cycle and 1b/cycle operation is presented in this paper. An effective and high speed comparator clock signal generation and transmission logic is proposed to accelerate the speed of SAR ADC. Besides compared with the previous multi-bit per cycle SAR ADC works that consume a lot of energy, the proposed architecture hybrid 2b/cycle operation and conventional 1b/cycle operation result in good balance between power consumption and speed. The simulation results show that the proposed ADC achieves a SNDR of 65.2dB near the Nyquist input frequency of the sampling rate of 350MS/s. It only consumes 1.2mW and achieves a FoM of 2.4fJ/conv-step.