Monolithic III-V/CMOS Co-integrated Technology, Scalable Compact Modeling, and Hybrid Circuit Design

This paper presents an overview of the essential elements in the SMART-LEES (Singapore MIT Alliance for Research and Technology - Low Energy Electronic Systems) research program, including monolithic III-V/CMOS co-integrated technology, unified device compact models with geometry/bias scalability, and monolithic III-V/Si process design kit for hybrid circuit design.