Design of low noise and low power Chopper Stabilized Amplifier for Neural Recording Applications

This paper presents a low noise and low power chopper stabilized amplifier for neural recording applications capable of handling 50mV DC offset voltage with only 1V supply voltage. Chopper modulation is introduced to suppress low-frequency noise and a DC servo loop is utilized to suppress electrode drift, achieving a low high-pass cut-off frequency point for noise suppression. Impedance boosting loop is employed to increase the input impedance. Moreover, fast settled duty-cycle switched resistors are implemented to realize extremely low bandwidth integrators and a stable high pass corner frequency in a few milliseconds. In this thesis, the overall circuits are simulated and validated using the CSMC 0.18um 1P6M CMOS process. the proposed chopper stabilized amplifier consumes 2.7 uW for each channel at 1 V and achieves a bandwidth of 0.5-35Hz and an input-referred noise of 4.5 uVrms.