Analog VLSI design of supervised-learnable neural cell using switched-current technique

This paper addresses the design of an analog very large-scale integration (VLSI) high accuracy neural cell with supervised learning ability using standard 2-/spl mu/m CMOS technology. A novel architecture is presented such that all cells, input, output, or hidden, have the same architecture which ensures a high degree of flexibility in terms of topology programming. Moreover, in designing the cell architecture, a new design technique based on hardware functionality multiplexing is employed. This technique resulted in a considerable compact cell. On the circuit level, the cell design is based mainly on a novel very high accuracy switched-current (SI) memory cell. With minor modifications, the SI memory cell is used in building all of the switched-current-based modules in the cell, which resulted in a high accuracy neural cell. The performance and timing for the separate modules and the whole cell are extensively studied. The cell is tested through a multi-layer perceptron network (MLP) using SPICE simulations to solve the digits-recognition problem.