A compact adaptive equalizer IC for HIPERLAN system

The design of a compact high-symbol-rate adaptive equalizer IC for the receiver of a high-speed local area network that meets the ETSI HIPERLAN standard is presented in this paper. Although the HIPERLAN defines a slowly time-varying multi-path fading-channel system, the Inter-Symbol Interference (ISI) problem is still very severe since its data rate is up to 23.5 Mbps. An Adaptive Decision Feedback Equalizer (ADFE) is selected to overcome this problem, however, the FIR filters of the ADFE require high hardware cost for complex-number computation. In this work, we select the sequential architecture to reduce the hardware cost. The penalty of adopting the sequential architecture is that several internal clocks with a much higher operating frequency (235 MHz) and the corresponding high-speed components are required. In order to generate internal clocks, we embed an All Digital Phase-Locked Loop (ADPLL) in this chip. Meanwhile, the design of high speed multipliers and adders are achieved based on the combination of PTL, CPL, and CPL-TG CMOS logic circuits. Finally, our ADFE chip is designed in a 3.3 V 0.35 /spl mu/m CMOS technology with only 3/spl times/2.8-mm/sup 2/ core area and 1 W power dissipation.