Building blocks for large annealed compact neural networks

In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.