An Effective Method For Hardware Multiplication Using Vedic Mathematics

Multiplication is an inevitable process for any computing system. It is also one of the basic arithmetic operations which require essentially more hardware resources and processing time than addition and subtraction. In real time systems, multiplication must be faster enough to meet the requirements and performance. This paper provides a detailed study regarding the performance of hardware algorithms for computers to achieve multiplication. The essence of the ancient method in multiplication is brought back through Vedic multiplication algorithm, which is compared with the Traditional pen and paper algorithm and Booth multiplication algorithm. Based on the parameters such as Time delay, Area and Memory utilization generated using the Xilinx-Spartan 7 FPGA family shows that the ancient method of Vedic algorithm performs better than the other algorithms.